1. Field of the Invention
The invention generally relates to memory. In particular, the invention relates to writing data to a magnetic random access memory (MRAM) device.
2. Description of the Related Art
Computers and other digital systems use memory to store programs and data. A common form of memory is random access memory (RAM), such as dynamic random access memory (DRAM) devices and static random access memory (SRAM) devices. DRAM devices and SRAM devices are volatile memories. A volatile memory loses its data when power is removed. For example, when a conventional personal computer is powered off, the volatile memory is reloaded through a boot up process when power is restored. In addition, certain volatile memories such as DRAM devices require periodic refresh cycles to retain their data even when power is continuously supplied.
In contrast to the potential loss of data encountered in volatile memory devices, nonvolatile memory devices retain data for long periods of time when power is removed. Examples of nonvolatile memory devices include read only memory (ROM), programmable read only memory (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), flash memory, and the like. Disadvantageously, conventional nonvolatile memories are relatively large, slow, and expensive. Further, conventional nonvolatile memories are relatively limited in write cycle capability and typically can only be programmed to store data about 10,000 times in a particular memory location. This prevents a conventional non-volatile memory device, such as a flash memory device, from being used as general purpose memory.
An alternative memory device is known as magnetic random access memory (MRAM). An MRAM device uses magnetic orientations to retain data in its memory cells. Advantageously, MRAM devices are relatively fast, are nonvolatile, consume relatively little power, and do not suffer from a write cycle limitation. There are at least three different types of MRAM devices, including giant magneto-resistance (GMR) MRAM devices, pseudo spin valve (PSV) MRAM devices, and magnetic tunnel junction (MTJ) or tunneling magneto-resistance (TMR) MRAM devices.
A GMR MRAM device separates at least two ferromagnetic layers with a metallic spacer layer, such as a copper spacer layer. Magnetic vectors in one layer are magnetically fixed or pinned, while the magnetic vectors of the other magnetic layer can be switched to change the magnetization direction. The resulting change in resistance is used to store data. A PSV MRAM device uses an asymmetric sandwich of the ferromagnetic layers and metallic layer as a memory cell so that the ferromagnetic layers do not switch at the same time. A hard layer is used to store data, and a soft layer is used to read the data. The cells of GMR MRAM devices and PSV MRAM devices can be arranged in arrays.
In an MTJ MRAM device, at least two ferromagnetic layers are separated by a thin insulating tunnel barrier, such as a layer of aluminum oxide. Electrons pass relatively more freely when the magnetic orientations of the layers are aligned and relatively less freely when the magnetic directions of the layers are not aligned. One exemplary configuration for an MTJ MRAM memory device is a “cross-point” memory array, which comprises a first set of parallel conductive lines covered by an insulating layer, over which lies a second set of parallel conductive lines, which are perpendicular to the first lines. One set of conductive lines is referred to as the “bit” lines, and the other set of conductive lines is referred to as the “word” lines. The magnetic memory cells are sandwiched between the bit lines and the word lines at their intersections.
In an exemplary digital device, such as a computer system, an MRAM device is typically electrically coupled to a bi-directional I/O bus. However, it will be understood that an MRAM device can be configured to be read only and that an MRAM device can also be electrically coupled to a processor, a CPU, or other control unit without the benefit of a bus. MRAM devices can also be integrated with processors, such as microcontrollers and other integrated circuits.
In a memory read cycle, a selected MRAM device places data on the bus to be read by a processor or by other components (e.g., a component that accesses the MRAM device using direct memory access (DMA)). In a memory write cycle, a selected MRAM device receives data from the bus and stores the data within magnetoresistive cells of a memory array.
In a conventional MRAM device, a wait state is inserted between a read cycle and a write cycle to avoid bus contention. While bus contention is desirably avoided, the wait state disadvantageously slows down the throughput of the MRAM device. As a result, the processing speed of the digital device utilizing the MRAM is reduced.